Hand-crafting analog circuits layout in Cadence.
This blog is to share the intuitions of analog circuit design with circuit design enthusiasts. This blog is managed by Sumit M Khalapure and Shubham Jain, Research Scholars of IIT Bombay
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[Solved] How to draw the small-signal model of PMOS transistor?
Small signal model of PMOS can be a nightmare for students and new analog designer. But in reality PMOS small signal model is identi...
![](https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhvcHsQQVKAT33JvXWwXSHdmcYwsFfIMlpx6fSy6jj0I1NAXIeLZvy3HXMnVN7Gik_FVjj79CEDnl33I0s2-4WbDccrdCrchnZrIQIEvkpbk8y0lzbUvApc6KxBh6aLEjaQP6szhlt4e1O/s200/Screenshot+from+2020-05-15+09-01-30.png)
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Small signal model of PMOS can be a nightmare for students and new analog designer. But in reality PMOS small signal model is identi...
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This video gives the step-by-step process of creating a common source amplifier circuit schematic and symbol in Cadence.
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Post layout simulation needs DRC, LVS and Parasitic Extraction. This video is a step-by-step guide to post-layout simulations.
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